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16-bit, 600+ msps d/a converter preliminary technical data ad9726 rev. prd information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent ri ghts of analog devices. trademarks and registered trademarks are the prop erty of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.326.8703 ? 2004 analog devices, inc. all rights reserved. features 600+ msps dac update rate 16/14/12/10-bit resolution family lvds interface with built-in 100-termination resistors single data rate and doub le data rate capability excellent dynamic performance sfdr = 65 dbc at 140 mhz imd = 75 dbc at 140 mhz differential current outputs: 2 ma to 20 ma C40c to +85c temperature range operation on-chip 1.20 v reference package: 80-lead thermally-enhanced tqfp versatile clock and data interface applications instrumentation and test wideband communications systems point-to-point wireless lmds pa linearization high resolution displays functional block diagram data formatter data clock formatter data sync. calibration reference spi clock distribution and control 16-bit dac sdio csb iouta ioutb fsadj refio sdo/sync_alrm sclk/sync_upd reset db[15:0]+ db[15:0]? dataclk_in+ dataclk_in? rext dataclk_out+ dataclk_out? clk+ clk? ddr 04540-0-001 figure 1 product description the ad9726 is a 16-bit digital-to-analog converter (dac) that utilizes an lvds interface to achieve conversion rates in excess of 600 msps. it is in a family of pin compatible converters that offers selection of 10-bit, 12-bit, 14-bit, and 16-bit resolution grades. all of the devices share the same interface options, small outline package, and pinout, providing an upward or downward component selection path based on performance, resolution and cost. product highlights ultralow noise and intermodulation distortion (imd) enable high quality waveform synthesis at intermediate frequencies up to 200 mhz. lvds receivers support sdr or ddr modes, with the maxi- mum conversion rate exceeding 600 msps. manufactured on a cmos process, the ad9726 uses a proprie- tary switching technique that enhances dynamic performance. the current output of the ad9726 can be easily configured for various single-ended or differential circuit topologies.
ad9726 preliminary technical data rev. prd | page 2 of 16 table of contents specifications..................................................................................... 3 dc specifications ......................................................................... 3 ac specifications.......................................................................... 4 digital specifications ................................................................... 5 digital timing information ........................................................ 5 absolute maximum ratings............................................................ 6 pin configuration and function description .............................. 7 serial port interface register maps ................................................ 9 definitions ....................................................................................... 11 typical performance curves ......................................................... 12 theory of operation ...................................................................... 13 lvds inputs ................................................................................ 13 data synchronization circuitry ............................................... 13 internal reference and full-scale output current................ 13 analog output ............................................................................ 14 spi port control ......................................................................... 14 general operation of the serial port interface ...................... 14 instruction byte .......................................................................... 14 serial port interface pin description....................................... 14 notes on serial port operation ................................................ 15 outline dimension......................................................................... 16 ordering guide .......................................................................... 16
preliminary technical data ad9726 rev. prd | page 3 of 16 specifications dc specifications table 1. t min to t max , avdd1, avdd2, dbvdd = 3.3 v, advdd, acvdd, clkvdd, dvdd = 2.5 v, i outfs = 20 ma, unless otherwise noted. specifications subject to change without notice parameter min typ max unit resolution 16 bits dc accuracy integral nonlinearity 1.5 lsb differential nonlinearity 0.75 lsb analog output offset error C1 1 %fsr gain error %fsr full scale output current 20 1.26 ma output compliance range 1.14 v output resistance tbd 1.25 kw output capacitance 0.1 tbd pf reference output reference voltage 1.2 v reference output current 100 na reference input reference input compliance range v reference input resistance 5 kw small signal bandwidth 0.5 mhz temperature coefficients offset drift tbd ppm of fsr/oc gain drift (with internal reference) tbd ppm of fsr/oc reference voltage drift tbd ppm/oc power supply 1 avdd1, avdd2 voltage range 3.3 v analog supply current (i avdd1 + i avdd2 ) 51 ma advdd voltage range 2.5 v acvdd ma voltage range 2.5 v analog supply current ( i advdd + i acvdd ) 9 ma clkvdd voltage range 2.5 v clock supply current (i clkvdd ) 20 ma dvdd voltage range 2.5 v digital supply current (i dvdd ) 69 ma dbvdd voltage range 3.3 v digital supply current (i dbvdd ) 20 ma nominal power dissipation (p dis ) 2 479 mw nominal power dissipation (p dis ) 3 1000 mw 1 supply currents measured under the following conditions: f dac = 200 msps, f out = 11 mhz, nominal power supply voltages 2 power dissipation measured unde r the following conditions: f dac = 200 msps, f out = 11 mhz, nominal power supply voltages 3 power dissipation measured unde r the following conditions: f dac = 600 msps, f out = 111 mhz, nominal power supply voltages
ad9726 preliminary technical data rev. prd | page 4 of 16 ac specifications table 2. t min to t maz , avdd1, avdd2, dbvdd = 3.3 v, advdd, acvdd, clkvdd, dvdd = 2.5 v, i outfs = 20 ma, unless otherwise noted. specifications subject to change without notice. parameter typ unit dynamic performance max dac output update rate (ddr) 600 msps max dac output update rate (sdr) 440 msps ac linearity spurious free dynamic rang e (sfdr) to nyquist (f out = 0 dbfs) f data = 260 msps, f out = 20 mhz 71 dbc f data = 260 msps, f out = 70 mhz 68 dbc f data = 260 msps, f out = 120 mhz 68 dbc f data = 400 msps, f out = 20 mhz 72 dbc f data = 400 msps, f out = 70 mhz 66 dbc f data = 400 msps, f out = 140 mhz 60 dbc f data = 600 msps, f out = 20 mhz tbd dbc f data = 600 msps, f out = 125 mhz tbd dbc f data = 600 msps, f out = 250 mhz tbd dbc two tone imd to nyquist (f out1 = f out2 = C6 dbfs) f data = 300 msps, f out1 = 26 mhz, f out2 = 27 mhz 89 dbc f data = 300 msps, f out1 = 100 mhz, f out2 = 101 mhz 80 dbc f data = 300 msps, f out1 = 126 mhz, f out2 = 127 mhz 80 dbc f data = 500 msps, f out1 = 26 mhz, f out2 = 27 mhz 90 dbc f data = 500 msps, f out1 = 100 mhz, f out2 = 101 mhz 78 dbc f data = 500 msps, f out1 = 126 mhz, f out2 = 127 mhz 76 dbc f data = 600 msps, f out1 = 26 mhz, f out2 = 27 mhz tbd dbc f data = 600 msps, f out1 = 126 mhz, f out2 = 127 mhz tbd dbc f data = 600 msps, f out1 = 250 mhz, f out2 = 251 mhz tbd dbc noise spectral density (nsd) f data = 500 msps, f out = 20 mhz, 0 dbfs C162 dbm/hz f data = 500 msps, f out = 20 mhz, C12 dbfs C165 dbm/hz f data = 500 msps, f out = 120 mhz, 0 dbfs C151 dbm/hz f data = 500 msps, f out = 120 mhz, C12 dbfs C161 dbm/hz cdma2000 adjacent channel leakage ratio (aclr) f data = 245.76 msps, if = 61.44 mhz tbd dbc f data = 491.52 msps, if = 122.88 mhz tbd dbc f data = 491.52 msps, if = 190 mhz tbd dbc wcdma adjacent channel leakage ratio (aclr), single carrier f data = 184.32 msps, if = 61.44 mhz 79 dbc f data = 245.76 msps, if= 61.44 mhz 79 dbc f data = 491.52 msps, if = 122.88 mhz 76 dbc f data = 491.52 msps, if = 190 mhz 74 dbc wcdma adjacent channel leakage ratio (aclr), four carrier f data = 184.32 msps, if = 61.44 mhz, 69 dbc f data = 368.64 msps, if = 92.16 mhz 67 dbc
preliminary technical data ad9726 rev. prd | page 5 of 16 digital specifications table 3. t min to t max , avdd1, avdd2, dbvdd = 3.3 v, advdd, acvdd, clkvdd, dvdd = 2.5 v , i outfs = 20 ma, unless otherwise noted. specifications subject to change without notice. parameter conditions min typ max unit digital inputs vcm = 0.875 v to 1.575 v differential logic 1 (put into footnote, and delete column?) 0.1 0.6 v differential logic 0 C0.6 C0.1 v logic 1 current 3.5 ma logic 0 current 3.5 ma differential input resistance 100 w differential input capacitance 3 pf data setup time (t ds ) 0.9 ns data hold time (t dh ) C0.3 ns data clock output delay ( t dco ) 2.4 ns serial control bus maximum sclk frequency (fsclk) 15 mhz minimum clock pulse width high (t pwh ) 30 ns minimum clock pulse width low (t pwl ) 30 ns maximum clock rise/fall time 1 ms minimum data/chip select set up time (t ds ) 25 ns minimum data hold time (t dh ) 0 ns maximum data valid time (t dv ) 30 ns reset pulse width 1.5 ns inputs (sdi, sdio, sclk, csb) logic 1 voltage 2.1 3 v logic 0 voltage 0 0.9 v logic 1 current C10 +10 a logic 0 current C10 +10 a input capacitance 5 pf sdio output logic 1 voltage drvddC0.6 v logic 0 voltage 0.4 v logic 1 current 30 50 ma logic 0 current 30 50 ma digital timing information 04540-0-002 clk db[15:0] dataclk_in dataclk_ou t t dco t dh t ds figure 2. single datarate (sdr) mode 04540-0-003 t dco t ds t dh t dh t ds clk db[15:0] dataclk_in dataclk_out figure 3. double datarate (ddr) mode
ad9726 preliminary technical data rev. prd | page 6 of 16 absolute maximum ratings parameter with respect to min max unit avdd1, avdd2, dbvdd acom1, acom2, dbcom C0.3 tbd v advdd, acvdd, clkvdd, dvdd adcom, accom, clkcom, dcom C0.3 tbd v acom1, acom2, dbcom acom1, acom2, dbcom C0.3 +0.3 v adcom, accom, clkcom, dcom adcom, accom, clkcom, dcom C0.3 +0.3 v refio, fsdaj acom1 C0.3 avdd1 + 0.3 v iouta, ioutb acom1 C1 avdd1 + 0.3 v db0-db15, db0-db15 dbcom C0.3 dbvdd + 0.3 v dataclkout, dataclkout dbcom C0.3 dbvdd + 0.3 v rext, clk+, clk- clkcom C0.3 clkvdd + 0.3 v sdo/sync_alrm, sdio, csb dbcom C0.3 dbvdd + 0.3 v sclk/sync, reset dbcom C0.3 dbvdd + 0.3 v ddr, spi_dis adcom C0.3 advdd + 0.3 v stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating on ly; functional operation of the device at these or any other conditions above those listed in the operational sections of this spec ification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd (electrostatic discharge) sensitive devi ce. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although this prod uct features proprietary esd protection circuitry, perma- nent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degrada- tion or loss of functionality.
preliminary technical data ad9726 rev. prd | page 7 of 16 pin configuration and function description 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 fsadj refio reset csb sclk/sync_upd sdo/sync_alrm dgnd dvdd db4? db4+ dbgnd clkvdd rext clkvdd clkgnd clk+ clk? clkgnd dgnd dvdd db15+ db15? db14+ db13+ db12+ db3? db3+ db2? db2+ db1? db1+ db0? db0+ db14? db13? db12? db11+ db11? dbvdd sdio ad9726 top view (not to scale) pin 1 identifier 04540-0-012 spi_dis iouta ioutb agnd1 avdd1 agnd2 avdd2 acgnd acvdd adgnd advdd ddr agnd1 avdd1 agnd2 avdd2 acgnd acvdd adgnd advdd dbgnd dbvdd dbgnd dbvdd db10+ db10? db9+ db9? db8+ db8? db7+ db7? db6+ db6? db5+ db5? dataclk_out+ dataclk_out? dataclk_in+ dataclk_in? figure 4. pin configuration table 4. pin function description pin no. name description pin no. name description 1 clkvdd clock supply voltage 41 dbgnd digital data supply common 2 rext bias resistor. sets dataclk_out drive strength. nominally 1 k ? to dbgnd 42 db4+ digital input bit 4Ctrue 3 clkvdd clock supply voltage 43 db4C digital input bit 4Ccomplement 4 clkgnd clock supply common 44 db3+ digital input bit 3Ctrue 5 clk+ clock inputCtrue 45 db3C digital input bit 3Ccomplement 6 clkC clock inputCcomplement 46 db2+ digital input bit 2Ctrue 7 clkgnd clock supply common 47 db2C digital input bit 2Ccomplement 8 dgnd digital common 48 db1+ digital input bit 1Ctrue 9 dvdd digital supply voltage 49 db1C digital input bit 1Ccomplement 10 db15+ digital input bit 15Ctrue 50 db0+ digital input bit 0Ctrue 11 db15C digital input bit 15Ccomplement 51 db0C digital input bit 0Ccomplement 12 db14+ digital input bit 14Ctrue 52 dvdd digital supply voltage 13 db14C digital input bit 14Ccomplement 53 dgnd digital common 14 db13+ digital input bit 13Ctrue 54 sdo/sync_alrm spi_dis = 1: data/clock synchronization alarm 15 db13C digital input bit 13Ccomplement 55 sdio spi serial data input/output 16 db12+ digital input bit 12Ctrue 56 sclk/sync_upd spi_dis = 1: data/clock synchronization update required 17 db12C digital input bit 12Ccomplement 57 csb spi chip select (active low) 18 db11+ digital input bit 11Ctr ue 58 reset hardware reset 19 db11C digital input bit 11Ccomplement 59 refio reference output, 1.2 v nominal 20 dbvdd digital data supply voltage 60 fsadj full-scale current adjust
ad9726 preliminary technical data rev. prd | page 8 of 16 pin no. name description pin no. name description 21 dbgnd digital data supply common 61 ddr spi_dis = 1: double data rate mode (active high) 22 db10+ digital input bit 10Ctrue 62 advdd analog supply voltage 23 db10C digital input bit 10Ccomple ment 63 adgnd analog supply common 24 db9+ digital input bit 9Ctrue 64 acvdd analog supply voltage 25 db9C digital input bit 9Ccomple ment 65 acgnd analog supply common 26 db8+ digital input bit 8Ctrue 66 avdd2 analog supply voltage 27 db8C digital input bit 8Ccomple ment 67 agnd2 analog supply common 28 dataclk_out+ data clock outputCtr ue 68 avdd1 analog supply voltage 29 dataclk_outC data clock outputCcomp lement 69 agnd1 analog supply common 30 dbvdd digital data supply voltage 70 ioutb dac current outputCcomplement 31 dbgnd digital data supply common 71 iouta dac current outputCtrue 32 dataclk_in+ data clock inputCtrue 72 agnd1 analog supply common 33 dataclk_inC data clock inputCcomple ment 73 avdd1 analog supply voltage 34 db7+ digital input bit 7Ctrue 74 agnd2 analog supply common 35 db7C digital input bit 7Ccompleme nt 75 avdd2 analog supply voltage 36 db6+ digital input bit 6Ctrue 76 acgnd analog supply common 37 db6C digital input bit 6Ccompleme nt 77 acvdd analog supply voltage 38 db5+ digital input bit 5Ctrue 78 adgnd analog supply common 39 db5C digital input bit 5Ccompleme nt 79 advdd analog supply voltage 40 dbvdd digital data supply voltage 80 spi_dis spi disable (active high)
preliminary technical data ad9726 rev. prd | page 9 of 16 serial port interface register maps table 5. mode control via spi port address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 comms 00 sdiodir datadir swrst sleep pdn reserved 1 reserved exref 01 reserved data 02 datafmt ddr dclkpoli dclkpolo disdclko syncman syncupd syncalrm 03 reserved 04 reserved 05 reserved 06 reserved 07 reserved 08 reserved 09 reserved 0a reserved 0b reserved 0c reserved version 0d reserved reserved reserved reserved version[3] version[2] version[1] version[0] calmemck 0e reserved reserved calmem[1] calmem[0] re served calckdiv[2] ca lckdiv[1] calckdiv[0] memrdwr 0f calstat calen xferstat xferen smemwr smemrd fmemrd uncal memaddr 10 memaddr[7] memaddr[6] memaddr[5] memaddr [4] memaddr[3] memaddr[2 ] memaddr[1] memaddr[0] memdata 11 reserved reserved memd ata[5] memdata[4] memdata[3] me mdata[2] memdata[1] memdata[0] 1 reserved registers should be set to logic 0 (low state) during a write operation, and masked (ignored) during a read operation . table 6. spi register definitions register bit direction default description commctrl(00) sdiodir 7 1 0 0: sdio pin configur ed for input only during data transfer 1: sdio pin configured for input or output during data transfer datadir 6 1 0 0: serial data uses msb first format 1: serial data uses lsb first format swrst 5 1 0 1: default all serial register bits, except address 00h sleep 4 1 0 1: dac output current off pdn 3 1 0 1: all analog and digital circuitry, except serial interface, off reserved 2 0 0 reserved reserved 1 0 0 reserved exref 0 1 0 0: internal bandgap reference datactrl(02) datafmt 7 1 0 0: twos complement input data format 1: unsigned binary input data format ddr 6 1 0 0: single data rate mode 1: double data rate mode dclkpoli 5 1 0 0: data latched on dataclkin rising edge 1: data latched on dataclkin falling edge dclkpolo 4 1 0 0: data latche d on dataclkout rising edge 1: data latched on dataclkout falling edge disdclko 3 1 0 0: dataclkout enabled 1: dataclkout disabled syncman 2 1 0 0: automatic synchronization initiated following a syncalrm 1: manual synchronization needed following a syncalrm
ad9726 preliminary technical data rev. prd | page 10 of 16 syncupd 1 1 0 0: data sy nchronization complete 1: initiate data synchronization syncalrm 0 0 0 0: data synchron izer does not require updating 1: data synchronizer requires updating version(0d) version[3:0] [3:0] 0 C hardware version identifier calmemck(0e) calmem [5:4] 0 00 calibration memory 00: uncalibrated 01: self calibration 10: factory calibration 11: user input calckdiv [2:0] 1 000 calibration clock divide ratio from channel data rate 000:/32 001:/64 110:/2048 111:/4096 memrdwr(0f) calstat 7 0 0 0: self calibration cycle not complete 1: self calibration cycle complete calen 6 1 0 1: self calibration in progress xferstat 5 0 0 0: factory memory transfer not complete 1: factory memory transfer complete xferen 4 1 0 1: factory memory transfer in progress smemwr 3 1 0 1: write static memory data from external port smemrd 2 1 0 1: read static memory to external port fmemrd 1 1 0 1: read factory memory data to external port uncal 0 1 0 1: use uncalibrated memaddr(10) memaddr [7:0] i/o 00000000 address of factory or static memory to be accessed memdata(11) memdata [5:0] i/o 000000 data for fa ctory or static memory access 1: external reference
preliminary technical data ad9726 rev. prd | page 11 of 16 definitions linearity error (also called inte gral nonlinearity or inl) linearity error is defined as the maximum deviation of the actual analog output from the ideal output, determined by a straight line drawn from zero-scale to full-scale. differential nonlinearity ( dnl) dnl is the measure of the variation in analog value, normalized to full-scale, and associated with a 1 lsb change in digital input code. monotonicity a d/a converter is monotonic if the output either increases or remains constant as the digital input increases. offset error the deviation of the output current from the ideal of zero is called offset error. for i outa , 0 ma output is expected when the inputs are all 0s. for i outb , 0 ma output is expected when all inputs are set to 1s. gain error the difference between the actual and ideal output span. the actual span is determined by the output when all inputs are set to 1s, minus the output when all inputs are set to 0s. output compliance range the range of allowable voltage at the output of a current-output dac. operation beyond the maximum compliance limits may cause either output stage saturation or breakdown, resulting in nonlinear performance. temperature drift temperature drift is specified as the maximum change from the ambient (25c) value to the value at either t min or t max . for offset and gain drift, the drift is reported in ppm of full-scale range (fsr) per degree celsius. for reference drift, the drift is reported in ppm per degree celsius. power supply rejection the maximum change in the full-scale output as the supplies are varied from minimum to maximum specified voltages. settling time the time required for the output to reach and remain within a specified error band about its final value, measured from the start of the output transition. glitch impulse asymmetrical switching times in a dac give rise to undesired output transients that are quantified by a glitch impulse. it is specified as the net area of the glitch in pv-s. spurious-free dynamic range the difference, in decibels, between the rms amplitude of the output signal and the peak spurious signal over the specified bandwidth. total harmonic distortion thd is the ratio of the rms sum of the first six harmonic com- ponents to the rms value of the measured fundamental. it is expressed as a percentage or in decibels (db). signal-to-noise ratio (snr) s/n is the ratio of the rms value of the measured output signal to the rms sum of all other spectral components below the nyquist frequency, excluding the first six harmonics and dc. the value for snr is expressed in decibels. adjacent channel power ratio (or acpr) a ratio in dbc between the measured power within a channel relative to its adjacent channel. lvds low voltage differential signaling. a differential logic specifi- cation that defines logic levels as approximately 350 mv (differential) over a common mode range of 0.875 v to 1.575 v. lvds is designed to achieve clock rates of up to 840 mhz.
ad9726 preliminary technical data rev. prd | page 12 of 16 typical performance curves sfdr (dbc) 50 60 70 80 90 80 60 20 40 0 100 120 140 160 f out (mhz) 04540-0-004 0dbfs ?6dbfs ?12dbfs figure 5. sfdr vs. f out at f dac = 400 msps 40 50 60 70 80 90 100 imd (dbc) 0 20 40 60 80 100 120 140 f out (mhz) 04540-0-006 ?6dbfs 0dbfs ?12dbfs figure 6. imd vs. f out at f dac = 500 msps ?170 ?168 ?166 ?164 ?162 ?160 ?158 ?156 ?154 ?152 ? 150 noises spectral density (dbm/hz) 0 20 40 60 80 100 120 140 f out (mhz) 04540-0-005 ?12dbfs 0dbfs figure 7. noise spectral density vs. f out at f dac = 500 msps 55 60 65 70 75 80 aclr (dbc) 1 carrier 61.44mhz if 184.32msps 4 carriers 61.44mhz if 184.32msps 4 carriers 92.16mhz if 368.64msps 04540-0-007 figure 8. wcdma aclr at select intermediate frequencies and sample rates
preliminary technical data ad9726 rev. prd | page 13 of 16 theory of operation lvds inputs the ad9726 uses lvds (low voltage differential signaling) digital inputs to enable high speed digital signaling. lvds allows the use of a differential signal for optimum noise reject- tion, and has small signal amplitude for fast speed and lower power dissipation. each differential digital input on the ad9726 has an internal 100 ? resistor for proper load termination. the lvds digital data inputs on the ad9726 meet the ieee reduced range (rr) specs for common mode input range (875 mv to 1575 mv) with an input differential threshold of 350 mv. data synchronization circuitry the high speeds at which the lvds digital interface is designed to operate require maintaining synchronization of the data (db[15:0]+, db[15:0]C) and data clock (dataclk_in+, dataclk_inC) with the dac clock (clk+, clkC). since the dac clock input is not lvds, the phase relationship between that clock and the data can vary, and, unless precautions are taken, data can be corrupted. the input data must be provided at the same frequency as the dac clock from an lvds source with an accompanying lvds data clock. since the dac and data clocks are different types, their phase relationship is difficult to specify. the ad9726 provides internal circuitry to keep the data from being corrupted over a wide variation in relative phase. once the dac and data clocks have been established and synchron- ization has been initiated, the phase between the two clocks can vary by at least one full clock cycle without loss of data. if the phase relationship between the clocks varies enough to cause a possible loss of data, the ad9726 can be resynchronized in several different ways. the internal synchronization ci rcuitry in the ad9726 eases this problem by allowing the phase to vary by at least one full clock cycle, once synchronization has been established. it does this by demultiplexing the incoming data stream into four channels, each containing every fourth data word. each of these words is present for four dac clock cycles. the data is then remulti- plexed by sampling each channel with the appropriate dac clock cycle. initial synchronization is established in one of the following ways: 1. when the reset pin is asserted, the synchronization logic is initiated to provide optimal internal timing. 2. if spi_dis is not asserted, the synchronization is optimized by writing setting sync_upd (02h[1]) high. 3. if spi_dis is asserted, the synchronization is optimized by asserting the sync_upd pin. once synchronization is established, the ad9726 needs to be reoptimized only if operating conditions change enough to affect the relative phase of the dac and data clocks by more than one clock cycle. the ad9726 detects when a synchroni- zation update is necessary, and indicates this need by asserting syncalrm (02h[0]) or sync_alrm high. if syncalrm (02h[0]) or sync_alrm have been asserted, resynchroni- zation can be accomplished as follows: 1. if the synchronization logic is in automatic mode (syncman (02h[2]) = 0), the synchronization logic will optimize the internal timing as necessary. two data words will typically be lost or repeated when an optimization occurs. if that possibility could cause serious problems, manual operation may be required. 2. if the synchronization logic is in manual mode (syncman (02h[2]) = 1), the logic will indicate the need for an update by asserting syncalrm (02h[0]) high. in normal operation, a logic high on syncalrm (02h[0]) does not mean that data is being lost, but that conditions are close to the point where data may be lost. optimization should be initiated by setting syncupd (02h[1]) high at a convenient time. 3. monitoring the synchronization logic state and initiating an update can be done via package pins by setting spi_dis high and using the sync_alrm and sync_upd pins in the same way the manual synchronization operation is described in step 2. note that syncupd (02h[1]) or sync_upd can be asserted at any time to optimize the synchronization, even if syncalrm (02h[0]) or sync_alrm have not indicated that it is necessary. if either the data clock or the dac clock is interrupted for any reason, a syncupd or sync_upd should be executed to insure that no subsequent data is lost. internal reference and full-scale output current the ad9726 contains an internal band gap reference of 1.2 v. the reference voltage is applied to an external resistor at fsadj, and the resultant current is amplified by the reference buffer to provide the full-scale current for the dac output. the gain equation from the internal reference to the dac output (assuming the digital inputs are at full scale) is as follows: i outfs = 1.2 32/fsadj taking into account the state of the digital inputs, the output current of i outa and i outb at any instant in time is: i outa = i outfs (db15:db0)/65536 i outb = i outfs (1 ? db15:db0)/65536
ad9726 preliminary technical data rev. prd | page 14 of 16 analog output the analog output of the ad9726 is based around a high dyna- mic range cmos dac core. the output consists of a different- tial current source capable of up to 20 ma full-scale. the output devices are pmos and are capable of sourcing current into an output termination within a compliance voltage range of 1 v. excellent distortion, noise, and aclr perfor-mance is achie- vable to nyquist at sample rates of 600 msps+. spi port control the ad9726 serial port is a flexible, synchronous serial com- munications port allowing easy interface to many industry standard microcontrollers and microprocessors. the serial i/o is compatible with most synchronous transfer formats, inclu- ding both the motorola spi and intel ssr protocols. the inter- face allows read/write access to all registers that configure the ad9726. single or multiple byte transfers are supported as well as msb first or lsb first transfer formats. the ad9726 serial interface port can be configured as a single pin i/o (sdio) or two unidirectional pins for in/out (sdio/sdo). general operation of the serial port interface there are two phases to a communication cycle with the ad9726. phase 1 is the instruction cycle, which is the writing of an instruction byte into the ad9726, and coincident with the first eight sclk rising edges. the instruction byte provides the ad9726 serial port controller with information regarding the data transfer cycle, which is phase 2 of the communication cycle. the phase 1 instruction byte defines the number of bytes in the data transfer, the starting register address for the first byte of the data transfer, and whether the upcoming data transfer is read or write. the first eight sclk rising edges of each com- munication cycle are used to write the instruction byte into the ad9726. a logic 1 on the cs pin followed by a logic 0 will reset the spi port timing to the initial state of the instruction cycle. this is true regardless of the present state of the internal registers or the other signal levels present at the inputs to the spi port. if the spi port is in the midst of an instruction cycle or a data transfer cycle, none of the present data will be written. the remaining sclk edges are for phase 2 of the communi- cation cycle. phase 2 is the actual data transfer between the ad9777 and the system controller. phase 2 of the communi- cation cycle is a transfer of 1, 2, 3, or 4 data bytes as determined by the instruction byte. normally, using one multibyte transfer is the preferred method. however, single byte data transfers are useful to reduce cpu overhead when register access requires 1 byte only. registers change immediately upon writing to the last bit of each transfer byte. instruction byte the instruction byte contains the information shown in table 7 table 7 n1 n0 description 0 0 transfer 1 byte 0 1 transfer 2 byte 1 0 transfer 3 byte 1 1 transfer 4 byte r/w bit 7 of the instruction byte determines whether a read or a write data transfer will occur after the instruction byte write. logic high indicates a read operation. logic 0 indicates a write operation. n1, n0 -bits 6 and 5 of the instruction byte determine the number of bytes to be transferred during the data transfer cycle. the bit decodes are shown in the following table: table 8 msb lsb i7 i6 i5 i4 i3 i2 i1 i0 r/w n1 n0 a4 a3 a2 a1 a0 a4, a3, a2, a1, a0 bits 4, 3, 2, 1, 0 of the instruction byte determine which register is accessed during the data transfer portion of the communi- cations cycle. for multibyte transfers, this address is the starting byte address. the remaining register addresses are generated by the ad9726. serial port interface pin description sclk (serial clock) the serial clock pin is used to synchronize data to and from the ad9726, and to run the internal state machines. the sclk maximum frequency is 15 mhz. all data input to the ad9726 is registered on the rising edge of sclk. all data is driven out of the ad9726 on the falling edge of sclk. csb (chip select) active low input starts and gates a communication cycle. it allows more than one device to be used on the same serial communications line. the sdo and sdio pins will go to a high impedance state when this input is high. chip select should stay low during the entire communication cycle. sdio serial data i/o. data is always written into the ad9726 on this pin. this pin, however, can be used as a bidirectional data line. the configuration of this pin is controlled by bit 7 of register address 00h. the default is logic 0, which configures the sdio pin as unidirectional.
preliminary technical data ad9726 rev. prd | page 15 of 16 sdo serial data out. data is read from this pin for protocols that use separate lines for transmitting and receiving data. in the case where the ad9726 operates in a single bidirectional i/o mode, this pin does not output data and is set to a high impedance state. msb/lsb transfers the ad9726 serial port can support both msb first and lsb first data formats. this functionality is controlled by register address 00h bit 6. the default is msb first. when this bit is set to active high, the ad9726 serial port is in lsb first format. that is, if the ad9726 is in lsb first mode, the instruction byte must be written from least significant bit to most significant bit. multibyte data transfers in msb format can be completed by writing an instruction byte that includes the register address of the most significant byte. in msb first mode, the serial port internal byte address generator decrements for each byte required of the multibyte communication cycle. multibyte data transfers in lsb first format can be completed by writing an instruction byte that includes the register address of the least significant byte. in lsb first mode, the serial port internal byte address generator increments for each byte required of the multibyte communication cycle. the ad9726 serial port controller address will increment from 1fh to 00h for multibyte i/o operations if the msb first mode is active. the serial port controller address will decrement from 00h to 1fh for multibyte i/o operations if the lsb first mode is active. 04540-0-008 cs instruction cycle data transfer cycle sclk sdio sdo r/w 16 (n) 15 (n) 14 13 12 11 10 d7 n d6 n d7 n d6 n d2 0 d1 0 d0 0 d2 0 d1 0 d0 0 figure 9. serial register interface timing msb first notes on serial port operation the ad9726 serial port configuration bits reside in bit 6 and bit 7 of register address 00h. it is important to note that the configuration changes immediately upon writing to the last bit of the register. for multibyte transfers, writing to this register may occur during the middle of communication cycle. care must be taken to compensate for this new configuration for the remaining bytes of the current communication cycle. 04540-0-009 cs instruction cycle data transfer cycle sclk sdio sdo 10 11 12 13 14 15 (n) 16 (n) r/w d0 0 d1 0 d2 0 d0 0 d1 0 d2 0 d6 n d7 n d6 n d7 n figure 10. serial register interface timing lsb first 04540-0-010 cs t ds t sclk t pwh t pwl t ds t dh instruction bit 7 instruction bit 6 sclk sdio figure 11. timing diagram for register write to ad9726 04540-0-011 cs t dv data bit n data bit n? 1 sclk sdo sdio figure 12. timing diagram for register read to ad9726 the same considerations apply to setting the reset bit in register address 00h. all other registers are set to their default values, but the software reset doesnt affect the bits in register address 00h. it is recommended to use only single byte transfers when changing serial port configurations or initiating a software reset.
ad9726 preliminary technical data rev. prd | page 16 of 16 outline dimension 0.15 0.05 0.27 0.22 0.17 0.20 0.09 0.50 bsc gage plane 0.25 7 3.5 0 1.05 1.00 0.95 1 20 21 41 40 60 80 61 pin 1 top view (pins down) 14.00 sq 12.00 sq seating plane 1.20 max 0.75 0.60 0.45 1 20 21 41 40 60 80 61 6.00 sq bottom view coplanarity 0.08 compliant to jedec standards ms-026-add-hd figure 13. 80-lead thin plastic quad flat package, exposed pad [tqfp/ed] (sv-80) dimensions shown in millimeters ordering guide model temperature range package description package option ad9726bsv -40c to +85c 80 lead tqfp sv-80 thermal characteristics thermal resistance 80-lead thermally enhanced tqfp package ja = 23.5c/w* *with thermal pad soldered to pcb. ? 2004 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. pr04540-0-1/04(prd)

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